Infineon Technologies's Munich Research Labs has extended present integrated circuit wiring to smaller feature sizes. The resulting wiring met electrical reliability requirements for future chip generations extending to the 2010 timeframe. The electrical assessment covered sub-70nm metal lines down to 40nm line widths, embedded in grooves of a dielectric film. Metal lines as narrow as 55nm are expected to be used for IC production in 2010.

The obtained maximum current densities in these copper lines were in the
80-100MA/cm2 regime. These densities exceed those known from today's most
advanced technologies by a factor of two to five. This extreme current
carrying capability is ascribed to very efficient heat transfer to the
intermetal dielectric surrounding the metal lines. The heat transfer to the
intermetal dielectric was achieved by a favourable ratio of surface to
cross-sectional area of the metal lines. The wires investigated had profile
heights exceeding the wire widths.
In an investigation of electromigration resistance, a mean time to failure
of sub-70nm copper lines of 80-90 years was obtained, a value comparable
with that for 180nm ICs.
The lithography tools needed for the fabrication of chip generations in the
2010-13 timeframe do not yet exist. Infineon used a spacer technique to
narrow the mask openings defined by manufacturing lithography tools for
pattern transfer into the dielectric film. The copper wires investigated
were fabricated with the damascene technique. The wafers were processed with
standard semiconductor manufacturing equipment and processes developed for
250nm ICs at International Sematech in Austin TX.